DocumentCode
2177841
Title
9 bit 3.3 M samples/s pipelined A-to-D converter using a new mismatch insensitive algorithm
Author
Ren, Yalin ; Leung, Bosco ; Lin, Yuh-Min
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume
1
fYear
1997
fDate
3-6 Aug 1997
Firstpage
253
Abstract
This paper presents the implementation and testing results for a pipelined analog-to-digital converter, using a new mismatch insensitive algorithm. The testing results show that the ADC resolves 9 bits at 3.3 M samples/s without any digital error correction
Keywords
analogue-digital conversion; monolithic integrated circuits; pipeline processing; 9 bit; A/D converter; analog/digital converter; capacitor mismatch; mismatch insensitive algorithm; pipelined ADC; Analog-digital conversion; Clocks; Energy consumption; Error correction; Fabrication; Switched capacitor circuits; Testing; Throughput; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location
Sacramento, CA
Print_ISBN
0-7803-3694-1
Type
conf
DOI
10.1109/MWSCAS.1997.666081
Filename
666081
Link To Document