Rapid and accurate timing simulation of radiation-hardened digital microelectronics using VHDL

The development of a fast, yet accurate, timing simulation capability based on VHSIC Hardware Description Language (VHDL) without the use of back annotation of timing delay information is presented. This simulator is intended, primarily, for use with radiation-hardened microelectronic circuits in simulating timing of circuit operation in the pre-radiation and post-radiation environment. Additionally, this simulator works well, using simplified models, for conducting timing estimates of circuit operation in cases where radiation effects are not a concern. Development of the timing models used in the VHDL timing simulator are presented. The timing models are based on a gate output drive capability being represented as an equivalent drive resistance. The loads of the driving gate and the input gates are correspondingly represented by equivalent capacitance values. The resultant gate delays are calculated from the drive resistance and the combined load capacitances. The implementation of the timing models are incorporated into a VHDL library composed of logic gates, latches, and flip-flops. Simulations of circuits were run in SPICE and VHDL to assess the timing accuracy and simulation run time of the VHDL-based timing simulator versus SPICE, and results are presented. Final evaluation of the simulator included testing of a microprocessor control unit. In all cases, the VHDL-based simulation runs over two orders of magnitude quicker than the equivalent SPICE simulation. In the pre- and post-radiation environment, accuracy estimates are usually within five percent and always within 12 percent