An architecture for high-order, variable polynomial analog Viterbi detectors

Author

Altarriba, Michael ; Spencer, Richard

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

1

fYear

1997

fDate

3-6 Aug 1997

Firstpage

268

Abstract

We show a convenient architecture for implementing the Viterbi Algorithm (VA) in terms of basic 4-node cells called meta units. This architecture can be used for high-order channel polynomials with arbitrary coefficients. By using the minimum node metric to control metric growth and selecting the proper path memory, a high-order Viterbi detector can be implemented in analog hardware with modest dynamic range and path memory requirements. The architecture required for implementing a 4th-order polynomial detector is discussed

Keywords

Viterbi detection; analogue processing circuits; polynomials; 4th-order polynomial detector; analog Viterbi detectors; analog hardware; arbitrary coefficients; dynamic range; high-order channel polynomials; meta units; minimum node metric; path memory requirements; variable polynomial detectors; Bit error rate; Computer architecture; Detectors; Equations; Maximum likelihood detection; Polynomials; Semiconductor device noise; Signal to noise ratio; Solid state circuits; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Conference_Location

Sacramento, CA

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.666085

Filename

666085