Design and implementation of high-speed Reed-Solomon decoder

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2^m) are implemented on the composite field GF(2²ⁿ) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 μm CMOS process.