The design and implementation of a shared packet buffer architecture for fixed and variable sized packets

Author

O´Kane, Stephen ; McKillen, Colm ; Sezer, Sakir

Author_Institution

Inst. of Electron., Commun. & Inf. Technol., Queen´´s Univ., Belfast, UK

fYear

2005

fDate

17-20 July 2005

Firstpage

352

Lastpage

356

Abstract

In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbit/s using standard FPGA technology.

Keywords

bandwidth allocation; buffer storage; field programmable gate arrays; packet switching; Altera Stratix 2 FPGA technology; buffer bandwidths; buffering; fixed sized packets; resource sharing; shared buffer circuit; shared packet buffer architecture; variable sized packets; Asynchronous transfer mode; Bandwidth; Circuits; Computer architecture; Field programmable gate arrays; IP networks; Internet; Packet switching; Routing; Switches; reg;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications, 2005. advanced industrial conference on telecommunications/service assurance with partial and intermittent resources conference/e-learning on telecommunications workshop. aict/sapir/elete 2005. proceedings

Print_ISBN

0-7695-2388-9

Type

conf

DOI

10.1109/AICT.2005.88

Filename

1517654