The design and implementation of a shared packet buffer architecture for fixed and variable sized packets

In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbit/s using standard FPGA technology.