Interleaved SAR ADC for in-pixel conversion in future X-ray FEL application

This work presents the design of an interleaved Successive Approximation Register (SAR) ADC, part of the readout channel for the PixFEL detector. The PixFEL project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging for application at the next generation free electron laser (FEL) facilities, through the adoption of cutting-edge microelectronic technologies and innovative design and architectural solutions. For this purpose, the collaboration is developing the fundamental microelectronic building blocks for the readout channel (low noise analog front-end with dynamic compression feature, high resolution and low power ADC, high density memories). This work focuses on the design of the ADC: to obtain a good tradeoff between power, conversion speed and area occupation, an interleaved SAR ADC architecture was adopted. The design is being carried out in a 65 nm CMOS technology. After schematic simulation at the maximum sample rate of 5 MHz, a maximum DNL = 0.125 LSB and a maximum INL = 0.138 LSB were obtained. None of them was found to exceed 0.5 LSB after post layout simulations. The SNR is 56.64 dB, which implies an ENOB = 9.6. The power consumption is 85 μW. Different test structures have been designed, with an area going from 0.00563 mm² to 0.0072 mm².