A high speed high resolution readout with 14-bits area efficient SAR-ADC adapted for new generations of CMOS image sensors

In this paper, a high speed high resolution readout design for CMOS image sensors is presented. It has been optimized to fit within a 7.5um pitch under a 0.28um 1P3M process. The readout design ensures one conversion in only 1.5us and targets a DNL feature about +0.9/−0.7 over 14-bits. Noise performances have been optimized as well to ensure an 84dB dynamic range image sensor. Along with the designing phase, image quality has been considered and corrected by means of analog and digital correlated-double-sampling (CDS) operations. Compactness of the design has been assured through a specific architecture of the analog-to-digital converter (ADC) making it compatible with fine pixel pitch design.