Analysis and implementation of a multilevel coded modulation scheme

The authors describe a multilevel coded modulation system for STM1 signaling (155.52 Mbit/s) with 28 MHz channel spacing. The main goal is to reach good performance while keeping decoding delay and computational complexity as low as possible. This is obtained by a two-level scheme based on the partition chain E₈/RE₈/2E₈. The outer codes are a rate-1/2 16-ary convolutional code and the singly-extended Reed-Solomon code seRS(16,14). The motivations behind the design choices are illustrated and the implementation on FPGA is presented. The authors conclude by analyzing the performance of the system and by showing experimental results.