• DocumentCode
    2178287
  • Title

    Sub-picosecond-jitter clock generation for interleaved ADC

  • Author

    Gong, Jianping ; McNeill, John A.

  • Author_Institution
    Electrical and Computer Engineering Department, Worcester Polytechnic Institute, Worcester, MA 01609
  • fYear
    2015
  • fDate
    June 29 2015-July 2 2015
  • Firstpage
    101
  • Lastpage
    104
  • Abstract
    This paper presents a design technique using a digitally-controlled delay line (DCDL) for the generation of sub-picosecond-jitter ADC sampling clock phases from a low-cost low-frequency clock source. In a test chip fabricated in a 0.18-μm CMOS technology, measured rms jitter is 0.28ps for each delay stage and 0.9ps through a 10 stage delay line.
  • Keywords
    Clocks; Delay lines; Delays; Jitter; Propagation delay; Semiconductor device measurement; Systematics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ph.D. Research in Microelectronics and Electronics (PRIME), 2015 11th Conference on
  • Conference_Location
    Glasgow, United Kingdom
  • Type

    conf

  • DOI
    10.1109/PRIME.2015.7251344
  • Filename
    7251344
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2178287