Ultra-reliable digital avionics (URDA) processor architecture

The objective of the URDA program is to develop a prototype advanced development model (ADM) processor that combines a data processor, signal processor, memory and system interface on a single SEM-E avionics card. TI´s approach integrates two Ada-programmable, URDA basic processor modules (BPMs) with a JIAWG-compatible PiBus and TMBus onto a common SEM-E format ADM module and provides a separate, high-speed (25-MWord/s 100-MByte/s) input/output bus for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400 MFLOPS vector processing in a removable multichip module (MCM). The URDA BPMs use the chipset and BPM architecture developed on the TI Aladdin program to implement a high-performance processor in an MCM package compatible with assembly onto standard form-factor, liquid-flow-through printed wiring board (PWB) modules. A Mips R4000 family reduced instruction set computer (RISC) processor and a TI 100-MHz bipolar complementary metal-oxide semiconductor (BiCMOS) vector co-processor (VCP) application-specific integrated circuit (ASIC) provide, respectively, the 100 MIPS of scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. Extensive software development, system modeling and simulation, and system integration and test tools are provided with the URDA processor