Architecture of a fault tolerant system for real time embedded applications

This paper aims to present a generalized fault tolerant architecture for time critical embedded systems where microprocessors/microcontrollers are used as basic processing elements. If such a system fails at any instant of time, a standby mechanism is required to take over the responsibility of task handling automatically, without affecting the processing of the tasks. The case of a digital telephony system may be cited as an example. If such a system becomes faulty and a standby unit takes the processing responsibility instantaneously or within a maximum allowable limit of time, then no call will be dropped. The proposed architecture is based on redundancy approach and a shadow of the main memory of a unit is kept so that the standby unit can access current data and status instantly. By introducing this type of approach restoration of processing can be achieved within a short interval of time. A monitoring logic is incorporated to monitor the health of the system continuously. It is assumed that this monitoring logic will work properly even if the other portions of the system fail.