Balanced current source model of the three-input combinational loigc gate for timing analysis

Current source model (CSM) has been considered as a promising candidate for the logic gate model used for the timing analysis of circuits with sub-90-nm CMOS technologies. Existing CSMs of the multiple-input combinational logic gates build lookup tables (LUTs) for the model parameters as functions of the voltages not only of input and output nodes, but also of selected internal nodes. These models can achieve high accuracy, but require a set of high-dimension LUTs. Besides, most existing CSMs were tested as single-stage, then the accuracy of the input capacitances were not well checked. This paper presents an extended CSM for the three-input combinational logic gates. The proposed CSM builds LUTs for the input current source, input capacitance, Miller capacitance, output current source, and output capacitance with dimensions of the input and output node voltages, excluding the internal node voltages. To better model the capacitance at the input node, a calibration capacitance is added at the input node. Experimental results with 32-nm technology show that the proposed CSM can achieve good accuracy while keeping dimensions of the LUTs low.