The design of 16×16 wave pipelined multiplier using fan-in equalization technique

In this paper, a wave-pipelined 16×16 multiplier is presented. The critical problem of wave pipelining, the cumulative delay deviation of each stage, is minimized by using fan-in equalization technique. A new logic cell concept, Tree Pass transistor Logic (TPL), is employed as a wave pipeline circuit element, whose speed is comparable to CPL, and whose logic style is similar to that of DPL. Also a new true single phase flip-flop is proposed which enables one to reduce the number of registers to a half of conventional wave pipeline configuration. The wave pipelined 16×16 multiplier of total 31,400 transistors, is comprised of input-fanin equalizer, 8 modified Booth´s encoder, 2 level of (4:2) compressor and 28 bit fast adder. At 3 V supply, the estimated throughput rate of 500 MHz is obtained by SPICE simulator using typical parameters of 0.8 μm technology and practical considerations