A 50 MHz 16-point FFT processor for WLAN applications

Author

Weste, N. ; Bickerstaff, M. ; Arivoli, T. ; Ryan, P.J. ; Dalton, J.W. ; Skellern, D.J. ; Percival, T.M.

Author_Institution

Electron. Dept., Macquarie Univ., Sydney, NSW, Australia

fYear

1997

fDate

5-8 May 1997

Firstpage

457

Lastpage

460

Abstract

This paper presents the architecture, design and implementation of a 50 MHz FFT processor for a high speed Wireless Local Area Network. The 110,000 transistor chip is implemented in 0.6 μm TLM CMOS and uses a custom design flow that allows the rapid design of high speed, high density and low power, process independent, DSP datapaths and related logic directly from a Verilog description

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital signal processing chips; fast Fourier transforms; integrated circuit design; wireless LAN; 0.6 micron; 50 MHz; DSP datapaths; FFT processor; TLM CMOS; Verilog description; WLAN applications; custom design flow; wireless local area network; Bandwidth; Communication industry; Digital signal processing chips; Hardware design languages; Modems; Modulation coding; Physics; Radio frequency; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606666

Filename

606666

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2178604