Phase locked loops for array processors

In modern computers the processor synchronization problem arises. In array processors the clock skew may be significant. The last may lead to the incorrect working of parallel algorithms. The problem of a clock skew in high-speed systems is so important that modern VLSI chips are often supplied by several phase locked loops, placed on one chip. In this case the phase locked loops can be used for creating a distributed system of generators. Here the discrete phase locked loop is considered.