Title :
A hardware performance analysis for a CAD tool for PLA testing
Author :
Cruz, Alfiedo ; Reilova, Rafael
Author_Institution :
Comput. Inf. Syst., EDP Coll. of Puerto Rico, Hato Rey, Puerto Rico
Abstract :
In this paper we present comparative performance for PLA logic/fault simulation and test pattern generation of the algorithms developed by Bose and Cruz, respectively. In the first section, the results of vectorization in a pipelined scientific machine are shown. Later, the algorithms are analyzed for hardware performance and a parallelization environment. Finally, results for the PLA growth fault test generation are shown
Keywords :
automatic testing; fault location; logic CAD; logic testing; performance evaluation; pipeline processing; programmable logic arrays; Bose; CAD tool; Cruz; PLA testing; comparative performance; fault test generation; hardware performance; hardware performance analysis; logic/fault simulation; parallelization environment; pipelined scientific machine; test pattern generation; time analysis; vectorization; Algorithm design and analysis; Computational modeling; Educational institutions; Fault detection; Hardware; Information systems; Optimized production technology; Performance analysis; Programmable logic arrays; System testing;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666120
