Design of a high-speed packet switch with fine-grained quality-of-service guarantees

Author

Bhagwan, Ranjita ; Lin, Bill

Author_Institution

Center for Wireless Commun., California Univ., San Diego, La Jolla, CA, USA

Volume

3

fYear

2000

fDate

2000

Firstpage

1430

Abstract

We present a new input-queued switch architecture designed to support deadline-ordered scheduling at extremely high-speeds. In particular, deadline-ordered scheduling is enabled through a combination of hardware-based sorted priority queues called P-heaps and a round-robin crossbar scheduler. The priority queues are implemented using a novel scalable pipelined heap-based architecture. Using a 0.35 micron CMOS standard-cell technology, we demonstrate a 32-port switch capable of sustaining 10 Gb/s line rates

Keywords

CMOS integrated circuits; electronic switching systems; packet switching; quality of service; queueing theory; 0.35 mum; 10 Gbit/s; CMOS standard-cell technology; P-heaps; deadline-ordered scheduling; fine-grained QoS guarantees; hardware-based sorted priority queues; high-speed packet switch design; input-queued switch architecture; line rates; quality-of-service guarantees; round-robin crossbar scheduler; scalable pipelined heap-based architecture; CMOS technology; Communication switching; Computer architecture; Data structures; Hardware; Packet switching; Quality of service; Scalability; Switches; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2000. ICC 2000. 2000 IEEE International Conference on

Conference_Location

New Orleans, LA

Print_ISBN

0-7803-6283-7

Type

conf

DOI

10.1109/ICC.2000.853733

Filename

853733