DocumentCode
2179266
Title
Built-in self-test of bit-serial arithmetic units for digital signal processing
Author
Kreken, Hans O. ; Aas, Einar J.
Author_Institution
Fac. of Electr. Eng. & Telecommun., Norwegian Univ. of Sci. & Technol., Tronheim, Norway
Volume
1
fYear
1997
fDate
3-6 Aug 1997
Firstpage
453
Abstract
Bit-serial multipliers with fixed coefficients are commonly exploited in area efficient DSP applications. Built-In Self-Test is a viable technique for high quality testing. We present and analyze a very area efficient BIST technique based on normal or inverted output-to-input feedback. Testing is employed at system speed
Keywords
built-in self test; circuit feedback; digital arithmetic; digital signal processing chips; fault diagnosis; area efficient DSP applications; bit-serial arithmetic units; built-in self-test; digital signal processing; fixed coefficients; high quality testing; inverted output-to-input feedback; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Digital arithmetic; Digital signal processing; Hardware; Output feedback; Scanning probe microscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location
Sacramento, CA
Print_ISBN
0-7803-3694-1
Type
conf
DOI
10.1109/MWSCAS.1997.666132
Filename
666132
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