Title :
A CMOS current-mode full-adder cell for multi-valued logic VLSI
Author :
Barton, R.J., III ; Walker, O., III ; Fouts, D.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
Abstract :
This paper describes the design and implementation of a carry save adder cell for multi-valued logic (module 4) VLSI using the HAMLET CAD tool. A VLSI test and evaluation integrated circuit was implemented with MAGIC, simulated using SPICE, and fabricated through the MOSIS service. Engineering modifications to the original current-mode inverter cells used by HAMLET were made leading to significant power savings in a complete design. The fabricated device performed as predicted by SPICE simulation
Keywords :
CMOS logic circuits; SPICE; VLSI; adders; carry logic; circuit CAD; current-mode logic; logic CAD; multivalued logic circuits; CMOS current-mode full-adder cell; HAMLET CAD tool; MAGIC; SPICE; carry save adder cell; multi-valued logic VLSI; power savings; Adders; Circuit simulation; Circuit testing; Design automation; Design engineering; Integrated circuit testing; Multivalued logic; Power engineering and energy; SPICE; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666134
