Maintaining System Signal and Power Integrity Characteristics as Part of a Module Cost-Reduction Exercise

Author

Dahlen, P.E. ; Timpane, T. ; Becker, D.J. ; Liang, T.W. ; Martin, W.D. ; Rudrud, P. ; Bartley, G.K.

Author_Institution

IBM Global Eng. Solutions, Rochester, MN

fYear

2007

fDate

29-31 Oct. 2007

Firstpage

83

Lastpage

86

Abstract

This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical properties and characteristics of the ceramic and organic package designs were not absolutely identical, it was necessary to perform electrical equivalency analyses at the system level.

Keywords

ceramic packaging; cost reduction; ASIC; ceramic-organic package design; electrical properties; module cost-reduction; organic laminate version; power integrity characteristics; system signal characteristics; Application specific integrated circuits; Ceramics; Conducting materials; Costs; Delay; Dielectric materials; Laminates; Packaging; Signal design; Timing; ceramic package; organic package; power integrity; signal integrity; system timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2007 IEEE

Conference_Location

Atlanta, GA

Print_ISBN

978-1-4244-0883-2

Type

conf

DOI

10.1109/EPEP.2007.4387130

Filename

4387130