The design and implementation of reconfigurable multiplier with high flexibility

Author

Shi, Jiangyi ; Jing, Gang ; Di, Zhixiong ; Yang, Si

Author_Institution

Key Lab. of Wide Band-gap Semicond. Mater. & Devices of Minist. of Educ., Xi Dian Univ., Xi´´an, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

1095

Lastpage

1098

Abstract

This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of the smallest multiplier-cells, the 4 bit multiplier. Synthesized results could reach as high as 425.53MHz using SMIC 0.13um CMOS technology library under the worst case condition.

Keywords

CMOS logic circuits; multiplying circuits; 4 bit multiplier; CMOS technology library; SMIC; frequency 425.53 MHz; generated multiplier operand; multiplier-cells; pipeline depth; reconfigurable mechanism; reconfigurable multiplier design; size 0.13 mum; word length 4 bit; Adders; Delay; Digital signal processing; Field programmable gate arrays; Hardware; IP networks; Pipelines; DSP; FPGA; MAC; multiplier; reconfigurable;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Zhejiang

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6066684

Filename

6066684