Design of multi-threaded processor´s pause mechanism

This paper presents three pause mechanisms of multi-threaded processors (micro-engine) of network processor, which is mainly used for dealing with reference instruction. We implement design of RTL-level code, functional simulation and logic synthesis on these three mechanisms. At last according to frequency and hardware resources and the expected performance requirements we select pause method based on state machine as the pause mechanism of micro-engine. This method ensures effective functional integrity of the micro-engine and meets prospective requirements of design.