An extended temperature range UHF RFID front-end in CMOS 350 nm

This paper describes the architecture and the transistor-level implementation of a UHF RFID front-end designed in CMOS 0.35μm technology with limited analog options to comply with EPC Class1/Generation2 standard. Since power acquisition is critical to RFID tag performance, two rectifier architectures are proposed and their performance is assessed by simulation in extended temperature range. In spite of technology constraints, good performance and low power consumption are obtained by the RFID front-end.