Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication

Author

Huang, Gang ; Bakir, Muhannad ; Naeemi, Azad ; Chen, Howard ; Meindl, James D.

Author_Institution

Georgia Inst. of Technol., Atlanta

fYear

2007

fDate

29-31 Oct. 2007

Firstpage

205

Lastpage

208

Abstract

Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting "decap" die and through-vias, are discussed in this paper.

Keywords

integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; power supply circuits; 3D chip stacks; 3D integration; analytical physical model; decap die insertion; design guidelines; power delivery; power supply noise; through-vias insertion; Analytical models; Capacitance; Circuit noise; Current supplies; Guidelines; Packaging; Power generation; Power supplies; Power system modeling; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2007 IEEE

Conference_Location

Atlanta, GA

Print_ISBN

978-1-4244-0883-2

Type

conf

DOI

10.1109/EPEP.2007.4387161

Filename

4387161