Basic concepts of HDLs: VHDL

Notwithstanding the powerful capabilities of Hardware Description Languages (HDLs) only a few designers actually use them. The main drawback for their acceptance has been the lack of a standard HDL able to cover the various levels of a design. The emergence of V(HSIC)HDL as the international standard HDL used in new and powerful CAD tools makes knowing it essential for any design engineer. The paper presents some design examples at different levels of abstraction and gives an introduction to basic concepts of VHDL. Considerations about the future trends of VHDL are analyzed. The main conclusions obtained are: the need to standardize design practices and packages for model sharing and the need to define some standard description styles and/or language subsets to be used in synthesis at different abstraction levels