Design and realization of small point FFT processor based on twiddle factor classification

In this paper, a new design method for small point fast Fourier transform (FFT) processor is proposed in order to satisfy the increased demands for low resource and power consumption in addition to high real-time performance in communication and control systems. Using 64 point FFT with radix-2, decimation in time (DIT) algorithm as the design objective, only an adder block and a multiplier block with pipeline structure and floating point arithmetic are adopted applying this design method. According to different classifications of twiddle factor, corresponding butterfly operations can be implemented to save the total calculation time to only 1100 clock cycles for 64 point FFT. In addition, multiple FFT processor blocks can be integrated for parallel computing to achieve higher data throughput rate. Compared with some other designs of 64 point FFT, the final results show that the proposed design has better real-time performance and lower system level complexity with the same amount of resources.