A parameterizable Handel-C neural network implementation for FPGA

Author

Benbouchama, C. ; Tadjine, M. ; Bouridane, A.

Author_Institution

E.M.P., Algiers

fYear

2009

fDate

21-23 May 2009

Firstpage

390

Lastpage

394

Abstract

This paper shows the design possibility of a parameterizable implementation of neural multi-layer network on FPGA circuits (Field Programmable Gate Array) through the use of Handel-C language. The algorithm used for the training is the back- propagation. The tools of implementation and synthesis are the DK 4 of Celoxica and the ISE 6.3 of Xilinx. The targeted components are XCV2000 on Celoxica RC1000 board and XC2V1000 on RC200. The representation of the real numbers in fixed point was used for the data processing. The realization of the activation function is made with the approximate polynomial. A high level environment was designed in order to specify and introduce architecture parameters.

Keywords

C language; backpropagation; electronic engineering computing; field programmable gate arrays; neural nets; C language; Celoxica RC1000 board; FPGA; Xilinx ISE 6.3; back propagation; data processing; field programmable gate array; parameterizable Handel-C neural network implementation; polynomial approximation; Backpropagation algorithms; Circuit synthesis; Computer science; Data processing; Field programmable gate arrays; Network synthesis; Neural networks; Neurons; Parallel architectures; Polynomials; FPGA; Handel-C; Neural Networks; Parameterizable implementation;

fLanguage

English

Publisher

ieee

Conference_Titel

Human System Interactions, 2009. HSI '09. 2nd Conference on

Conference_Location

Catania

Print_ISBN

978-1-4244-3959-1

Electronic_ISBN

978-1-4244-3960-7

Type

conf

DOI

10.1109/HSI.2009.5091011

Filename

5091011