In-Situ Characterization of High-Speed I/O Chip-Package Systems

Author

Ahn, Jongshick ; Puligundla, Sudeep ; Bashirullah, Rizwan ; Fox, Robert M. ; Eisenstadt, William R.

Author_Institution

Dept. of Elec. & Comp. Eng., Florida Univ., Gainesville, FL

fYear

2007

fDate

29-31 Oct. 2007

Firstpage

311

Lastpage

314

Abstract

This paper reports methods of signal integrity model validation for high-speed I/O chip-package systems including simultaneous switching noise, package power/ground noise and crosstalk. IBIS-models of I/O chip performance are extracted from measurements using high impedance probes. IBIS macro model based SPICE simulations and onboard measurements are compared to optimize package model over a several GHz range. A characterization IC including differential CMOS current-mode logic, (CML) and single-ended, Gunning transceiver logic, (GTL) I/O were designed with TI 65 nm digital CMOS processes. Key CMOS CML characterization data is used to investigate the effects of the package on signal integrity performance and GTL data will be forthcoming.

Keywords

CMOS digital integrated circuits; SPICE; chip scale packaging; current-mode logic; integrated circuit modelling; integrated circuit noise; Gunning transceiver logic; I/O chip-package systems; IBIS model; SPICE simulations; crosstalk; differential CMOS current-mode logic; digital CMOS processes; ground noise; high impedance probes; input/output buffer information specification; package power noise; signal integrity model validation; simultaneous switching noise; size 65 nm; CMOS logic circuits; CMOS process; Crosstalk; Impedance measurement; Integrated circuit noise; Logic design; Packaging; Power system modeling; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2007 IEEE

Conference_Location

Atlanta, GA

Print_ISBN

978-1-4244-0883-2

Type

conf

DOI

10.1109/EPEP.2007.4387189

Filename

4387189