Study of High Speed Current Excitation Reverse Engineering Methodology Using Measured Voltage and PDN Impedance Profile from a Running Microprocessor

Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.