A new parallel algorithm for CRC generation

Author

Joshi, Sanjay M. ; Dubey, Pradeep K. ; Kaplan, Marc A.

Author_Institution

Maryland Univ., Baltimore, MD, USA

Volume

3

fYear

2000

fDate

2000

Firstpage

1764

Abstract

Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. A new parallel algorithm for CRC generation and its software as well as hardware implementation is described. For the software implementation, this paper has focused on the 32-bit CRC used in the Ethernet, computed on a general purpose PowerPC microprocessor with the new AltiVec technology. A speedup by a factor of 4.57 over the standard table-lookup algorithm was obtained. A hardware implementation of the algorithm is then discussed, which yields an unlimited speed-up potential over the bit-wise serial algorithm

Keywords

error detection; general purpose computers; local area networks; microprocessor chips; parallel algorithms; 32 bit; AltiVec technology; CRC generation; Ethernet; bit-wise serial algorithm; cyclic redundancy check; digital communications; error-detection schemes; general purpose PowerPC microprocessor; hardware implementation; parallel algorithm; software; software implementation; speedup; standard table-lookup algorithm; Computer architecture; Cyclic redundancy check; Hardware; Internet; Kernel; Microprocessors; Parallel algorithms; Protocols; Spine; Trademarks;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2000. ICC 2000. 2000 IEEE International Conference on

Conference_Location

New Orleans, LA

Print_ISBN

0-7803-6283-7

Type

conf

DOI

10.1109/ICC.2000.853801

Filename

853801