DocumentCode :
21811
Title :
Novel Designed SiC Devices for High Power and High Efficiency Systems
Author :
Mikamura, Yasuki ; Hiratsuka, Kenji ; Tsuno, Takashi ; Michikoshi, Hisato ; Tanaka, Shoji ; Masuda, T. ; Wada, Kazuyoshi ; Horii, Taku ; Genba, Jun ; Hiyoshi, Toru ; Sekiguchi, Takeshi
Author_Institution :
Power Device Div., Sumitomo Electr. Ind., Ltd., Osaka, Japan
Volume :
62
Issue :
2
fYear :
2015
fDate :
Feb. 2015
Firstpage :
382
Lastpage :
389
Abstract :
Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (Dit) of 3 × 1011 cm2 eV-1, which causes the high channel mobility of 80 cm2 V-1 s-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 mQ cm2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 mQ cm2 and the blocking voltage of 3850 V are obtained for 3300 V application.
Keywords :
epitaxial layers; ion implantation; power MOSFET; semiconductor doping; silicon compounds; wide band gap semiconductors; 4H-silicon carbide MOSFETs; MOS interface; SiC; V-groove trench MOSFET; buried p+ regions; double implanted MOSFET; edge termination region; epitaxial layer; field-limiting rings; high channel mobility; high efficiency systems; high power systems; interface state density; junction FET region; junction termination extension; silicon carbide devices; size 6 mm; very low channel resistance; voltage 1700 V; voltage 3300 V; voltage 3850 V; Epitaxial layers; Face; Logic gates; MOSFET; Resistance; Silicon carbide; Switches; (0-33-8) face; 4H-silicon carbide (SiC); MOSFET; V-groove trench; V-groove trench.; buried p+ region; buried p+ region; channel mobility; field-limiting ring (FLR); junction FET (JFET); junction termination extension (JTE);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2014.2362537
Filename :
6942216
Link To Document :
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