DocumentCode
2181686
Title
Framework for fast prototyping of applications running on reconfigurable system on chip
Author
Viktorin, Jan ; Korcek, Pavol ; Kosar, V. ; Korenek, Jan
Author_Institution
Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic
fYear
2013
fDate
8-10 Oct. 2013
Firstpage
347
Lastpage
348
Abstract
Recently introduced chips with ARM based processors and programmable logic provide huge potential for digital signal processing, networking and other applications. Many IP cores and operating systems have been prepared for these chips to simplify the development process. Nevertheless, the integration of IP cores and operating system is not covered by any development tool yet. Developers have to design, implement and debug the communication between hardware and software part of the application. Therefore we propose Reconfigurable System on Chip (RSoC) Framework to support rapid prototyping of applications running on FPGA chips with a processor. The framework consists of FPGA logic and OS drivers to support communication between application core in the FPGA and application software on the host processor. Moreover, the framework allows to configure automatically address space of components in the FPGA and supports dynamic loading of drivers according to the FPGA configuration. The developer can focus only on the application software and accelerating core. For demonstration purposes, the framework is exploited in the example of a video processing application, where an image filter is running in the software and than is accelerated in the FPGA.
Keywords
field programmable gate arrays; multiprocessing systems; programmable logic devices; signal processing; system-on-chip; ARM based processors; FPGA chips; FPGA logic; IP cores; RSoC; digital signal processing; fast prototyping framework; image filter; operating systems; programmable logic; reconfigurable system on chip; video processing application; Bridges; Field programmable gate arrays; Hardware; IP networks; Software; Streaming media; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2013 Conference on
Conference_Location
Cagliari
Type
conf
Filename
6661569
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