DocumentCode
2181808
Title
Prototype of a novel steady-state load identification technique for digitally controlled DC-DC power supplies
Author
Congiu, Andrea ; Barbaro, Massimo ; Picciau, Andrea ; Bodano, Emanuele ; Hammerschmidt, Dirk
Author_Institution
DIEE - Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, Italy
fYear
2013
fDate
8-10 Oct. 2013
Firstpage
355
Lastpage
356
Abstract
This demo will show a novel method of Selftuning technique suitable for digitally controlled Switching Mode Power Supplies (SMPS). Perturbations can be added in order to stimulate loop reaction, which mainly contains load information. Variations on the Power Supply output filter, can be monitored and regulation gains can be consequently set for reaching a well compensated closed loop condition. The closed-loop system can be periodically perturbed by injecting a further amount of quantization noise provided through a low-resolution Delta-Sigma (ΔΣ) modulator. Digital control, PSD computation and Extraction-regulation blocks are synthesized on Virtex6 FPGA, while analog blocks (Buck Converter and ADC) are part of a Test Chip (TC) which can be configured via SPI in order to enable an external control loop configuration.
Keywords
DC-DC power convertors; adaptive control; closed loop systems; delta-sigma modulation; digital control; field programmable gate arrays; perturbation techniques; quantisation (signal); self-adjusting systems; switched mode power supplies; ΔΣ modulator; ADC; PSD computation; SMPS; Virtex6 FPGA; analog blocks; buck converter; closed loop condition; closed-loop system; control loop configuration; digital control; digitally controlled DC-DC power supply; digitally controlled switching mode power supply; extraction-regulation blocks; load information; low-resolution delta-sigma modulator; perturbations; power supply output filter; quantization noise; selftuning technique; steady-state load identification technique; test chip; Digital control; Modulation; Noise; Power electronics; Power supplies; Silicon; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2013 Conference on
Conference_Location
Cagliari
Type
conf
Filename
6661573
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