Finite element stress analysis of 3D TSV stack subject to large temperature loading

As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip area, Through silicon via (TSV) is introduced to replace the large number of long interconnects needed in previous 2D structure. However, the thermal-mechanical reliability problems of TSVs, such as interfacial delamination, via cracking and so on, have become a serious reliability concern. In this paper, finite element method (FEM) was employed to analyze the thermal-mechanical behavior of 3D-TSV stacks on different substrates. The thermal-mechanical response of 3D TSV stack using underfills is also investigated. It is found that the stress profile varies with geometric parameters such as edge distance and via diameter, while the underfills and substrate materials also have a significant effect.