Multiple-Symbol Parallel Interpolation in All-Digital Receiver

An earlier paper [1] introduced the theory of the single-symbol parallel interpolation in all-digital receiver, in which the interpolation is based on a scale of symbol, characterized by vector-operation of the vector input, fractional delay, and output. In this paper, the theory of the multiple-symbol parallel interpolation in all-digital receiver is proposed, in which the interpolation is based on a scale of frame, characterized by matrix-operation of the matrix input, fractional delay, and output. This trait dramatically lightens the hardware-constraint to the processing rate of the interpolator and in turn, greatly improves the processing speed of the receiver. Besides, with a vector frame clock whose every element corresponds to a symbol in the frame, the performance loss of the multiple-symbol parallel interpolation compared to the serial interpolation is only the loss introduced by the delay of timing loop, which is inevitable for structures of parallel interpolation.