DocumentCode
2182242
Title
The roundoff noise analysis for block digital filters realized in cascade form
Author
Chong, Uipil ; Kim, Soon-jong
Author_Institution
Dept. of Electr. Eng., Polytech. Univ., Brooklyn, NY, USA
fYear
1996
fDate
18-21 Nov 1996
Firstpage
282
Lastpage
285
Abstract
The block processing algorithm is suitable for high speed implementation of digital filters on parallel processing systems. Roundoff noise is guided via the internal structure of the block filter using a state variable formulation. In this paper, we calculate and compare output roundoff noise gain for various block filter structures, which have not been investigated yet
Keywords
VLSI; cascade networks; digital filters; parallel architectures; roundoff errors; block digital filters; cascade form; high speed implementation; internal structure; parallel processing systems; roundoff noise analysis; state variable formulation; Digital arithmetic; Digital filters; Equations; IIR filters; Lattices; Parallel processing; Quantization; Transfer functions; Vectors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-3702-6
Type
conf
DOI
10.1109/APCAS.1996.569271
Filename
569271
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