Title :
A 4.8-GHz Fully Integrated CMOS Integer-N PLL Frequency Synthesizer for WLAN
Author :
Hu, Kangmin ; Xiaofeng Yi ; Zhou, Ye ; Huang, Yumei ; Hong, Zhiliang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
fDate :
Oct. 18 2006-Sept. 20 2006
Abstract :
In this paper, a 4.8 GHz fully integrated low power, low phase noise phase-locked loop (PLL) frequency synthesizer ready for WLAN application is presented. It is implemented in a 0.18 mum IP6M CMOS process. The chip consumes only 16 mA (including local buffers to the receiver and transmitter) from a 1.8 V supply and occupies an area of 1.85times1.1 mm2. From measurements, its in-band phase noise is -55.8 dBc/Hz and out-of-band phase noise is -119 dBc/Hz at 3 MHz offset. With the help of digital controlled capacitor array (DCCA) this frequency synthesizer can lock from 4.2 - 4.82 GHz
Keywords :
CMOS integrated circuits; field effect MMIC; frequency synthesizers; integrated circuit noise; phase locked loops; phase noise; wireless LAN; 0.18 mum; 1.8 V; 4.8 GHz; CMOS integer-N PLL frequency synthesizer; IP6M CMOS process; PLL; WLAN; digital controlled capacitor array; in-band phase noise; local buffers; out-of-band phase noise; CMOS process; Digital control; Frequency synthesizers; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Semiconductor device measurement; Transmitters; Wireless LAN; LC VCO; Low Power; PLL; RF CMOS; wireless LAN (WLAN);
Conference_Titel :
Communications and Information Technologies, 2006. ISCIT '06. International Symposium on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9741-X
Electronic_ISBN :
0-7803-9741-X
DOI :
10.1109/ISCIT.2006.339844
