A 100MHz dual port (DP) MRAM with swing-less bit-line sensing (SLBS) operation for high-end microcomputer systems

Author

Li, Hu ; Okamura, Leona ; Yoshihara, Tsutomu ; Ooishi, Tsukasa ; Kihara, Yuji

Author_Institution

Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka

fYear

2006

fDate

Oct. 18 2006-Sept. 20 2006

Firstpage

63

Lastpage

66

Abstract

In this paper, we propose two kinds of implementations of the dual port MRAM, one of which is for the read/write concurrent operation while another is for the additional simultaneous read operation. Compared with dual port SRAM, the dual port MRAM accompanied with smaller memory cell size will make high performance systems realized in the mobile/robotics field. A swing-less bit-line sensing (SLBS) technique and the static bitline level in the read mode, help to realize the high performance under the condition of V_cc=1.0 V and the operation frequency of 100 MHz

Keywords

SRAM chips; magnetoresistive devices; microcomputers; 1.0 V; 100 MHz; dual port MRAM; high-end microcomputer systems; magnetoresistive random access memory; memory cell size; mobile-robotics field; read-write concurrent operation; simultaneous read operation; static bitline level; swing-less bit-line sensing operation; Batteries; Cache memory; Decoding; Frequency; Microcomputers; Mobile robots; Production systems; Random access memory; Robot sensing systems; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technologies, 2006. ISCIT '06. International Symposium on

Conference_Location

Bangkok

Print_ISBN

0-7803-9741-X

Electronic_ISBN

0-7803-9741-X

Type

conf

DOI

10.1109/ISCIT.2006.339888

Filename

4141514