Printed circuit board electrical design for wafer-level packaging

Wafer-level packaging is truly the next generation advanced chip-scale packaging technology. The main advantage of the wafer-level packaging is a smaller, thinner and lighter package with the minimized electrical length and smaller inductance. This paper presents a printed circuit board electrical design to assemble a wafer-level package of a wireless radio core. The link impact and challenges are addressed on both time domain and frequency domain for this high speed differential sub-system. The high density interconnect substrate is analyzed using design of experiment technique to test the significance of structured variation and its effects in the whole model. Results are obtained using electromagnetic solver and channel simulation. We also compare its signal integrity and power delivery performance with a similar design, but much thicker using flip-chip package mounted on top of the conventional board. The thin board for wafer-level packaging provides better power delivery and signal performance than the traditional assembly.