• DocumentCode
    2183723
  • Title

    16-channel two-parallel reed-solomon based forward error correction architecture for optical communications

  • Author

    Ji, Wenjie ; Zhang, Wei ; Peng, Xingru ; Liang, Zhibin

  • Author_Institution
    School of Electronic Information Engineering, Tianjin University, China
  • fYear
    2015
  • fDate
    21-24 July 2015
  • Firstpage
    239
  • Lastpage
    243
  • Abstract
    This paper presents a high-efficiency two-parallel Reed-Solomon (RS) decoder based on the compensated simplified reformulated inversionless Berlekamp-Massey (CS-RiBM) algorithm. To achieve high speed and low hardware complexity, the key equation solver (KES) block is designed by pipelining and folding processing. With TSMC 90nm process, the simulation results reveal that the 16-Channel proposed architecture can operate up to 625MHz and achieve a throughput rate of 156 Gbps with a total gate count of 269,000. The area of the proposed decoder is at least 35.6% fewer with the same technology, which meets the demands of next generation short-reach optical systems.
  • Keywords
    Clocks; Computational modeling; Computer architecture; Logic gates; Reed-Solomon codes; folding; optical communication systems; pipelined;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Signal Processing (DSP), 2015 IEEE International Conference on
  • Conference_Location
    Singapore, Singapore
  • Type

    conf

  • DOI
    10.1109/ICDSP.2015.7251867
  • Filename
    7251867