Title :
A new synthesis efficient, high density and high speed ORCA FPGA
Author :
Singh, Satwant ; Britton, Barry ; Spivak, Carolyn ; Nguyen, Ho ; Leung, Wai-Bor ; Andrews, Bill ; Powell, Gary ; Albu, Remus ; He, Jianshe ; Stuby, Rick ; Chin, Mou-Lin ; Chiu, Pin-Lin ; Steward, Jim ; Rabold, Doug
Author_Institution :
Lucent Technol., Microelectronics Group, Allentown, PA, USA
Abstract :
This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level “functions”, in addition to regular digital “logic”. It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration
Keywords :
field programmable gate arrays; flip-flops; high level synthesis; network routing; table lookup; ORCA 3C/3T; PAL-type decoder block; behavioral-level functions; fast hierarchical connections; flip-flops; high density FPGA; high speed ORCA FPGA; high-level logic synthesis; look-up tables; microprocessor interface; programmable clock manager; programmable interconnections; system-level features; twin-nibble fashion; Counting circuits; Field programmable gate arrays; Helium; Integrated circuit interconnections; Logic arrays; Logic devices; Programmable control; Programmable logic arrays; Routing; Table lookup;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606685
