Title :
A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability
Author :
Costello, J. ; Balicki, J. ; Bocchino, V. ; Chan, M. ; Nishiwaki, K. ; Nouban, B. ; Tran, N. ; Vest, B. ; Wong, M.
Author_Institution :
Altera Corp., San Jose, CA, USA
Abstract :
A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 μm triple layer metal process to produce a 55 kmil2 die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved
Keywords :
CMOS logic circuits; PLD programming; frequency multipliers; programmable logic devices; 0.5 micron; 140 MHz; 5.1 ns; CMOS PLD; built-in frequency multiplier; high density PLD; in-system programmability; programmable logic device; selectable frequency multiplication; triple layer metal process; Clocks; Costs; Frequency conversion; Logic devices; Macrocell networks; Pins; Programmable logic arrays; Programmable logic devices; Testing; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-3669-0
DOI :
10.1109/CICC.1997.606686
