Title :
Accuracy analysis of layout parasitic extraction based on Boolean methods
Author :
Brambilla, Anyelo ; Mancini, Paolo
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fDate :
31 May-3 Jun 1998
Abstract :
Layout parasitic extraction methods based on Boolean operation of layers are well established in design practice. They are developed on hypotheses that the layout can be considered as a two dimensional structure and that net capacitances depend only on the net area and perimeter values. In the paper, we show with the aid of layout structures that these hypotheses are now not valid for submicron layout technology and thus relevant errors are introduced in the estimation of the net capacitances
Keywords :
Boolean algebra; VLSI; capacitance; circuit layout CAD; integrated circuit layout; Boolean methods; layout parasitic extraction; net area; net capacitances; perimeter values; submicron layout technology; two dimensional structure; Clocks; Delay; Design methodology; Dielectrics; Laplace equations; Microelectronics; Paper technology; Parasitic capacitance; Routing; Signal design;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706959
