Hardware efficient transform designs with cyclic formulation and subexpression sharing

This paper presents a hardware efficient architecture for transform designs. Unlike other designs that use systolic array and memory-based design, the proposed architecture exploited the constant property of the transform coefficients as well as their numerical property. The proposed design reformulates the transform with cyclic convolution such that filter type subexpression sharing can be applied to reduce the area cost. The results show that the new designs can save up to 81% gate area cost compared with previous designs for 5-point DFT designs