Pulse-width-modulation feedforward neural network design with on-chip learning

Author

Bor, Jenn-Chyou ; Wu, Chum-Yu

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1996

fDate

18-21 Nov 1996

Firstpage

369

Lastpage

372

Abstract

In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under ±0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network

Keywords

CMOS integrated circuits; VLSI; feedforward neural nets; integrated circuit design; learning (artificial intelligence); mixed analogue-digital integrated circuits; neural chips; pulse width modulation; speech recognition; CMOS VLSI design; Chinese word speech classification; dynamic range; feedforward neural network design; function correctness; input pulse widths; linearity; mixed-mode circuits; multiplication functions; on-chip learning; pulse-width-modulation; summation functions; synapses; Circuits; Dynamic range; Feedforward neural networks; Linearity; Network-on-a-chip; Neural networks; Pulse measurements; Pulse width modulation; Space vector pulse width modulation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-3702-6

Type

conf

DOI

10.1109/APCAS.1996.569292

Filename

569292