Cost-radius balanced spanning/Steiner trees

The most crucial factor that degrades a high speed VLSI is the signal propagation delay in a routing tree. It is estimated additively by the amount of the source-to-sink path length and total length. To design a routing tree in which these two are balancingly small, we propose an algorithm to construct a spanning tree, by which a tree is constructed in a hybrid way of the Minimum-Tree and Shortest-Path Tree algorithms. The idea is extended to finding such a rectilinear Steiner tree. Experiments are given to show how the source-to-sink path length and total length are balanced and small