Title :
An optimal pin assignment algorithm with improvement of cell placement in standard cell layout
Author :
Wakabayashi, Shin´ichi ; Kishimoto, Yoshihisa ; Koide, Tetswhi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
Abstract :
In this paper, we propose an optimal pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density by assigning nets to terminals of cells. If the number of possible terminal assignments for each cell is bounded by some constant r, then the proposed algorithm runs in linear time. In most practical cases, the value of r is relatively small, and thus the proposed algorithm is effective and efficient to reduce the chip area
Keywords :
cellular arrays; circuit layout CAD; integrated circuit layout; logic CAD; network routing; cell placement; channel density; chip area; linear time; optimal pin assignment algorithm; standard cell layout; terminal assignments; Desktop publishing; Law; Legal factors; Routing; Wire;
Conference_Titel :
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-3702-6
DOI :
10.1109/APCAS.1996.569295