DocumentCode
2185056
Title
An improved hierarchical placement technique using clustering and region refinement
Author
Kim, Woniong ; Kim, Kitaek ; Shin, Hyunchul
Author_Institution
Dept. of Electron. Eng., Hanyang Univ., Ansan, South Korea
fYear
1996
fDate
18-21 Nov 1996
Firstpage
393
Lastpage
396
Abstract
An effective hierarchical placement technique has been developed based on improved clustering and region refinement algorithms. The region refinement algorithm has been developed for an efficient and effective iterative improvement of row-based cell placement. For efficiency, the placement refinement is performed using multiple levels of hierarchy and “closely connected” cells are clustered. The physical layout area containing cells is hierarchically partitioned into bins. In the region refinement algorithm, each bin becomes the active bin by turns and the placement is optimized by moving cells between the active bin and its neighbor bins. To obtain optimal placement results, partitioning and region refinement algorithms are performed several times at each hierarchical level. Several standard cell benchmark circuits from MCNC are placed using the suggested placement technique and about 8% better results have been obtained when compared with TW7.0
Keywords
circuit layout CAD; integrated circuit layout; IC layout; clustering algorithm; hierarchical partitioning; hierarchical placement technique; region refinement algorithm; row-based cell placement; standard cell benchmark circuits; Central Processing Unit; Circuit simulation; Clustering algorithms; Constraint optimization; Cost function; Delay estimation; Iterative algorithms; Partitioning algorithms; Shape; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-3702-6
Type
conf
DOI
10.1109/APCAS.1996.569298
Filename
569298
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