Employing radiation hardness by design techniques with commercial integrated circuit processes

Author

Mavis, David G. ; Alexander, David R.

Author_Institution

Microelectron. Div., Mission Res. Corp., Albuquerque, NM, USA

Volume

1

fYear

1997

fDate

26-30 Oct 1997

Firstpage

2.1

Abstract

Though process hardening remains the preferred method for achieving radiation hardness in high density integrated circuits (ICs), recent investigations into the hardness of specially designed gate array cells fabricated in a commercial 0.81 μm CMOS fabrication process have demonstrated greater than 100 krads (Si) total ionizing dose hardness, no single event latchup, and single event upset LET (linear energy transfer) (LET) thresholds greater than 50 MeV-cm²/mg. This work suggests that it is possible to achieve inexpensive ASICs (Application Specific Integrated Circuits) of modest complexity and radiation tolerance with commercial IC processes

Keywords

CMOS integrated circuits; CMOS logic circuits; application specific integrated circuits; integrated circuit design; leakage currents; radiation hardening (electronics); space vehicle electronics; 0.8 micron; 100 krad; CMOS fabrication process; application specific integrated circuits; commercial IC processes; design techniques; gate array cells; high density integrated circuits; inexpensive ASICs; linear energy transfer thresholds; radiation hardness; radiation tolerance; single event latchup; single event upset; space system electronics; Application specific integrated circuits; CMOS integrated circuits; CMOS process; Fabrication; Ionizing radiation; Low earth orbit satellites; Microelectronics; Protons; Radiation effects; Radiation hardening;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Avionics Systems Conference, 1997. 16th DASC., AIAA/IEEE

Conference_Location

Irvine, CA

Print_ISBN

0-7803-4150-3

Type

conf

DOI

10.1109/DASC.1997.635027

Filename

635027