Hardware implementation of a real-time distributed video decoder

Distributed video coding (DVC), based on Slepian-Wolf Theorem and/or Wyner-Ziv Theorem, was proposed to apply for the situation with little encoding and big decoding. We design and implement a distributed video decoder which is majorly composed of low-density parity-check accumulate (LDPCA), correlation noise modeling, soft input computation, and side information creation. Our proposed DVC decoder architecture, implemented in TSMC 90nm GUTM process technology, can meet the requirement of decoding a QCIF video with a speed of 30fps. The maximum operating frequency of the designed chip is 100MHz, the chip area is 4.67 mm², and the gate count is 690K.