• DocumentCode
    2185931
  • Title

    Hardware implementation of a real-time distributed video decoder

  • Author

    Yang, Hsin-Ping ; Ho, Meng-Hsuan ; Hsieh, Hsiao-Chi ; Cheng, Po-Hsun ; Chen, Sao-Jie

  • Author_Institution
    Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
  • fYear
    2015
  • fDate
    21-24 July 2015
  • Firstpage
    659
  • Lastpage
    664
  • Abstract
    Distributed video coding (DVC), based on Slepian-Wolf Theorem and/or Wyner-Ziv Theorem, was proposed to apply for the situation with little encoding and big decoding. We design and implement a distributed video decoder which is majorly composed of low-density parity-check accumulate (LDPCA), correlation noise modeling, soft input computation, and side information creation. Our proposed DVC decoder architecture, implemented in TSMC 90nm GUTM process technology, can meet the requirement of decoding a QCIF video with a speed of 30fps. The maximum operating frequency of the designed chip is 100MHz, the chip area is 4.67 mm2, and the gate count is 690K.
  • Keywords
    Decoding; Interpolation; Noise; Pins; Rate-distortion; Distributed Video Decoder; LDPCA Decoder; Side Information Creation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Signal Processing (DSP), 2015 IEEE International Conference on
  • Conference_Location
    Singapore, Singapore
  • Type

    conf

  • DOI
    10.1109/ICDSP.2015.7251957
  • Filename
    7251957
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2185931